1. Field of Invention
The present invention relates to a semiconductor device and its method of operation. More particularly, the present invention relates to a double-bit non-volatile memory (NVM) unit and a data read/write method for the double-bit NVM unit.
2. Description of Related Art
Non-volatile memory (NVM) is a type of fast access, miniature, power-saving, vibration-resistant and permanent storage media. Thus, the applications of NVM are wide. A prominent type of NVM is the flash memory. One major aspect of the flash memory is the capacity for block-by-block data erasure so that time is saved.
FIG. 1 is a schematic cross-sectional view showing the structure of a conventional non-volatile memory cell. As shown in FIG. 1, the non-volatile memory cell includes a stacked gate structure 110 over a substrate 100. A source/drain region 120 is formed in the substrate 100 on each side of the stacked gate structure 110. The stacked gate structure 110 further includes, from bottom to top, a tunnel oxide layer 112, a floating gate 114, an inter-gate dielectric layer 116 and a control gate 118. During programming, electrons are injected into the floating gate 114. To erase data, a high negative bias voltage is applied to the control gate 118 and hence electrons are channeled away from the floating gate 114.
However, in order to remove all electrons from the floating gate 114, over-erase of the aforementioned non-volatile memory cell often occurs. In other words, too many electrons may be forced out of the floating gate 114 during erasure, resulting in the accumulation of some positive charges in the floating gate 114. In the presence of excess positive charges, an inversion of the channel underneath the floating gate 114 may occur and ultimately this may lead to a permanent opening of the channel and possible data read errors.
To resolve the issue, a split gate structure is developed. FIG. 2 is a schematic cross-sectional view of a non-volatile cell having a conventional split-gate structure. As shown in FIG. 2, a split-gate structure 210 is formed over a substrate 200. A source/drain region 220 is formed in the substrate 200 on each side of the split gate structure 210. The split-gate structure 210 includes, from bottom to top, a tunnel oxide layer 212, a floating gate 214, an inter-gate dielectric layer 216, a control gate 218 and a transfer gate 218a. The transfer gate 218a extends from the control gate 218 to the side of the floating gate 214. In addition, both the transfer gate 218a and the floating gate 214, as well as the transfer gate 218a and the substrate 200, are separated by the inter-gate dielectric layer 216. In this type of design, the channel under the transfer gate 218a is opened up only when a voltage is applied to the control gate 218/transfer gate 218a. Hence, even if the channel underneath the floating gate 214 is permanently opened due to over-erase, the two source/drain regions 220 of the memory cell are still in a non-conductive state, thereby preventing data read errors.
Although the split-gate structure 210 is able to prevent errors due to over-erase, the design has an adverse effect on miniaturization. This is because the transfer gate 218a needs to occupy extra area. In addition, the combined width of the control gate 218 and the transfer gate 218a inside the split-gate structure 210 is different from the floating gate 214. The floating gate 214 and the control gate 218/transfer gate 218a must be patterned in two separate photolithographic processes. Consequently, alignment problems between the floating gate 214 and the control gate 218/transfer gate 218a may occur, leading to possible overlapping area errors between the control gate 218/transfer gate 218a and the floating gate 214. Ultimately, electrical performance of each memory cell may be different and control of the memory cells may be difficult.
Accordingly, one object of the present invention is to provide a double-bit non-volatile memory cell capable of preventing over-erase problems. The cell includes a substrate, a pair of stacked gates, a doped region, a source region and a drain region. Each stacked gate includes, from bottom to top, a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate. The doped region is located in the substrate between the two stacked gates. The source/drain regions are formed in the substrate on each side of the stacked gate pair. The source/drain regions and the doped region are doped identically.
This invention also provides a method of programming the said double-bit non-volatile memory cell. To write data into the first floating gate of the first stacked gate, a bias voltage is applied to the first and the second control gate of the first and the second stacked gate respectively. The channel underneath the first and the second floating gate is opened. In the meantime, a different bias voltage is applied to the respective source/drain regions so that electrons flow from the channel underneath the second floating gate to the channel underneath the first floating gate. The electrons obtain sufficient energy and produce hot electrons that are injected into the first floating gate.
This invention also provides an alternative method of programming the said double-bit non-volatile memory cell. To write data into the first floating gate of the first stacked gate, a higher bias voltage is applied to the first control gate of the first stacked gate. In the meantime, a lower bias voltage is also applied to the source/drain region on one side of the first stacked gate so that electrons move into the first floating gate via the source/drain region.
This invention also provides an alternative method of reading data from the said double-bit non-volatile memory cell. In this memory cell, the threshold voltage (the voltage at the control gate when the channel of the stacked gate is opened) of the channel underneath any stacked gate in the erased state is referred to as a first threshold voltage. Threshold voltage of the channel underneath any stacked gate in the written state is referred to as a second threshold voltage. The second threshold voltage is higher than the first threshold voltage. To read data stored in the first floating gate of the first stacked gate, a read bias voltage is applied to the first control gate of the first stacked gate. The read bias voltage is higher than the first threshold voltage but lower than the second threshold voltage. In the meantime, a transfer bias voltage is applied to the second control gate of the second stacked gate. The transfer bias voltage is higher than the second threshold voltage so that the channel underneath the second floating gate is forced open. Whether the first floating gate is in the written state or not is determined by the channel between the respective source/drain regions. If the channel between the source/drain region is conductive, data has not been written into the first floating gate. On the contrary, if the channel is non-conductive, data has been written into the floating gate.
The double-bit non-volatile memory of this invention uses two stacked gates but only a pair of source/drain regions. Therefore, a conductive channel is formed joining the two source/drain regions only when the channel underneath both the first and the second floating gates is opened. Since the probability of having both floating gates over-erased is small, the chance of maintaining a permanent channel between the source/drain terminals is slim. Thus, errors in data determination are greatly reduced. Moreover, one of the stacked gates can be regarded as a transfer gate because the transfer gate actually prevents the other transfer gate from being over-erased.
In addition, the double-bit memory cell is capable of holding two binary bits with one stacked gate serving as the transfer gate of the other stacked gate. Unlike the cell of a conventional split-gate having an additional transfer gate on one side of the control gate, the area for holding each bit is smaller. Furthermore, unlike a conventional split-gate design that demands a patterning of the floating gate before patterning the control gate and the transfer gate together, one stacked gate serves as the transfer gate of the other stacked gate in this invention. Hence, the floating gate and the control gate may be produced by a self-alignment method so that any non-conformity between different electrical devices is minimized.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.